Verilog Code For Serial Adder Subtractor

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--D. Thiebaut 11:03, 24 April 2012 (EDT)

This lab should be done after the introduction lab on Verilog. It shows how to use two modules, one for the basic 3-bit full-adder (adding a to b with carry-in), and one that uses 4 of them to create a 4-bit adder with an output carry.

• 1Full-Adder in Verilog
  • 1.7Generate a Test Module
• 2A 4-Bit Adder
  • 2.1New Verilog Module

Review

A full adder is a combinational logic that takes 3 bits, a, b, and carry-in, and outputs their sum, in the form of two bits, carry-out, and sum.

The figure below illustrates the circuit:

New Project

• The first task is start the Xilinx ISE and create a New Project. Let's call it FourBitAdder.
• Once the Project is created, add a New Source, of type Verilog Module. Call it SingleStage. It will contain the full-adder for 2 bits.
• Define the ports as follows:
  • a, input
  • b, input
  • cin, input
  • s, output
  • cout, output

We now have several options to define this adder. One is functional, as illustrated in the next subsection. Next is a logical description, where we express the outputs in terms of their logical equation. The final is a gate level description. Pick the one that seem most interesting to you. They should all yield the same result in the next section, where we test them.

Functional Description of Full Adder

Logical Description of Full Adder

• Complete the code of the module so that it looks like this:

Gate-Level Description of Full Adder

Check Module for Syntax Errors

• Click on the module file and select it in the Implementation window, and
• In the Process window, below the implementation window, double click on Synthesize, in the Implement Design menu.
• You should get this message in the console:

(If not, fix the bugs and retry!)

Generate a Test Module

• Add a New Source to the project, of type Verilog Test Fixture.
• Call it test.
• Specify SingleStage as the target of the testing.
• Edit the test.v file as illustrated below:

Some explanations

integer i

this is necessary since we have a loop that is going 8 times

initial begin

an initial block is done only once, at the beginning of the simulation. Here we make sure all the signals are 0 when we start.

always @ ( a or b or cin )

an always block means that whenever a or b or cin are modified the inside of the block should be evaluated. In essence we mean that whatever is in this block is dynamic and should be evaluated at any signal change.

#10 {a, b, cin} = i

After a delay of 10 ns, we take the bits that form the integer i (by default an integer contains 32 bits) and assign the lower ones to the three bits a, b, and cin. It's an easy way to generate a truth table.

#10 $stop

10 ns after the loop has terminated, stop the simulation.

Simulation

• Click on the Simulation button at the top of the Design Window,
• Select test.v as target
• Click on Behavioral Check Syntax and fix any bugs you may have.
• Finally, double click on Simulate Behavioral Model
• Verify that you obtain a timing diagram that demonstrates the correct operation of your adder:

Better Simulation Output

The timing diagram is fine, but a bit hard to read. A simpler test would be to have the simulation print out the value of the signals. This can be done by calling the predefined $monitor( ) function that will print to the console whenever there is a change in any of the signals.

Simply add the $monitor statement inside the always block:

Rerun the simulation and observe the output in the console of the ISim application:

We will now create a new Verilog module called MultiStages.v to create a full 4-bit adder.

The idea is simple. Best firewire audio interface. We want to add a 4-bit word to another 4-bit word and get a 4-bit sum, and a carry out.

New Verilog Module

All we need to do is write Verilog code that will replicate the full-adder encapsulated in SingleStage 4 times, and let the carry ripple from one stage to the next.

• Create a New Source of type Verilog Module and call it MultiStage
• Its ports should be defined as follows:

• Edit the code of the new module and replicate the code showed below:

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• Check the syntax of your module and fix any bugs you discover!

Explanations

wire cin
assign cin = 1'b0

The first stage of the adder, the one adding the Least Significant bits should have a 0 coming in on its carry-in input. This is done by creating this wire, which we set equal to 0 all the time in the next statement. The 1'b0 notation means 1 bit, with binary value 0.

SingleStage( .. .cout( ripple1 )..)
SingleStage( .. .cin( ripple1 ) ..)

The carry-out of one stage is directly connected to the carry-in of the next stage. We need a wire for this purpose. We could have defined ripple1 as a wire, but Verilog allows one to not declare wires that are internal to the circuit, connecting one block to another.

Test Module

• Add a New Source file of type Verilog Test Fixture and call it test4.
• Attach it to MultiStages
• Edit the module as shown below:

You should be able to recognize the main features of the test module by now. The one that might be surprising is the for loop. The 16 * 16 terms simply means that we want to test all the combinations of a added to b. Since a and b are 4 bits, each can be one of 16 possible configurations, hence 16 * 16.

• Check the Behavioral Syntax of your module and fix bugs if necessary.
• RUn the Behavioral Simulation Module
• Verify that you get an output similar to the one illustrated below.